1. Field of the Invention
The present invention relates to a method, apparatus, and program product for an automatic cell placement and wire routing between cells in designing the layout of integrated circuit.
2. Description of the Related Art
Coupling capacitance and coupling inductance between signal lines cause mutual interference (crosstalk), with a result that the signal waveforms are deformed to generate false signals. Miniaturization in elements of LSI makes easier the occurrence of crosstalk and leads to increase in time to correct a layout in an automatic cell placement and wire routing between cells.
FIGS. 9 and 10 are flowcharts showing a prior art an automatic cell placement and wire routing between cells process.
(S1) Cells are automatically placed in a frame on the basis of data of a net-list and a cell library so as to obtain an optimum value of an evaluation function.
(S2) Automatic routing between cells is performed on the basis of data of the net-list and the cell library.
(S3) Determined are resistance and capacitance values of laid-out wiring.
(S4) A check is made for each signal input of each cell as to whether signal is dulled due to resistance and capacitance of wiring connected to the signal input and the input/output capacitance of the cell, that is, as to whether there is a slew rate error that slew rate of the input signal is lower than a predetermined value.
(S5) If there is one judged to be a slew rate error, then the process goes to step S8, or else, goes to step S6.
(S6) A static timing analysis (STA) is performed for each flip flop.
(S7) If a timing error is detected in this STA, then the process goes to step S8, or else, goes to step S9.
(S8) A buffer cell is inserted in each line connected to a signal input of a cell in which the error is detected. Here, when there is no sufficient space to insert the buffer cell, its neighboring cells or lines are moved to secure a space. The process returns to step S3 to perform again an error check for each portion affected by insertion of a buffer cell or movement of cells or lines.
(S9) A check is made as to whether there is a parallel-wire length error (crosstalk error) that the wire length of parallel lines which are spaced less than a predetermined interval from each other is more than a predetermined value.
(S10) If this crosstalk error exists, then the process goes to step S13, or else, goes to step S11.
(S11) Taking into consideration the delay of signal propagation caused by coupling of capacitance and inductance between the lines in parallel, the STA is performed for each flip flop connected to one end or both ends of the lines in parallel.
(S12) If a timing error is detected in this STA, then the process goes to step S13, or else the process is completed.
(S13) A buffer cell(s) is inserted in each of the lines in parallel connected to the error-detected cell, or the interval between the lines in parallel is widened (spacing is performed). Here, when there is no sufficient space to insert the buffer cell, its neighboring cells or wiring is moved to secure the space.
(S14) Calculation is made for obtaining resistance and capacitance values of wiring that are changed in layout in step S13. The process returns to step S9 so as to perform again checks of steps S9 and S11 for portions in which the error is detected and which are affected by the error.
However, for example, if one of the lines in parallel is moved in order to resolve the crosstalk error, a new crosstalk may occur between the moved line and its neighboring one, and therefore, the processes of steps S9 to S14 of FIG. 10 are repeated several times in general, causing a problem of increasing turn around time of development (turn around time).
In addition, there is a need to determine the frame size of chip in advance with taking into consideration of the increase of layout space due to the spacing between the lines in parallel or insertion of buffer cells. This leads to occurrence of useless regions, tending to increase in chip size more than necessary.
Similarly, such problems occur also in connection with a self-wire length error.